Exemplary embodiments of the present invention relate to technology of fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a gate electrode of a poly-metal structure.
Recently, there has been introduced a gate electrode of a structure where a poly-silicon (Si) layer and a metal layer having low resistance and a high melting point, such as a tungsten (W) layer, are sequentially stacked (i.e., forming a so-called poly-metal structure), to provide operational properties that a highly integrated semiconductor device requires. The gate electrode of the poly-metal structure that is widely used recently has a poly-Si/WN/W structure where the poly-Si layer, a tungsten nitride (WN) layer and the W layer are sequentially stacked. At this time, the WN layer is used as a barrier metal layer to prevent a reaction from occurring between the W layer and the poly-Si layer during processes performed on the gate electrode.
Meanwhile, a process of forming a gate pattern by selectively etching a gate structure, including the poly-Si layer, the WN layer, and the W layer that are sequentially stacked on a gate insulation layer, generates micro-trench and plasma damage in the gate insulation layer. Therefore, a gate re-oxidation process is performed to cure the damage of the gate insulation layer, and a capping layer is formed on sidewalls of the W layer and the WN layer to prevent the W layer and the WN layer from being oxidized in the re-oxidation process.
FIGS. 1A to 1C are cross-sectional views illustrating a method for fabricating a conventional semiconductor device including a gate electrode of a poly-metal structure.
Referring to FIG. 1A, a first pattern 101 is formed by sequentially forming a gate insulation layer 12, a poly-Si layer 13, a WN layer 14 and a W layer 15 on a substrate 11, etching the W layer 15 and the WN layer 14 using a gate hard mask layer 16 on the W layer 15 as an etch barrier, and then partially etching the poly-Si layer 13.
Subsequently, a nitride layer 17 for a capping layer (later formed) is deposited along the surface of a resultant structure including the first pattern 101.
Referring to FIG. 1B, a capping layer 17A is formed on both sidewalls of the first pattern 101 by performing an overall etching process, e.g., an etch-back process, on the nitride layer 17.
Then, a second pattern 102 is formed by etching the remaining portion of the poly-Si layer 13 using the gate hard mask layer 16 and the capping layer 17A as an etch barrier. At this time, the second pattern 102 is usually referred to as a gate pattern. Hereinafter, the etched poly-Si layer is represented by reference numeral ‘13A’.
Referring to FIG. 1C, a gate re-oxidation process is performed to cure plasma damage and micro-trench generated in the gate insulation layer 12 that is exposed when forming the second pattern 102. By performing the gate re-oxidation process, an oxide layer 18 is formed on both sidewalls of the etched poly-Si layer 13A at the same time the damage to the gate insulation layer 12 is cured.
However, referring to FIG. 1A, the poly-Si layer 13 of the first pattern 101 has a sidewall S of a negative slope as a result of the difference of the etch selectivity of the W layer 15 and the WN layer 14 in comparison to the poly-Si layer 13. The sidewall S having a negative slope is formed when performing the etching process for forming the first pattern 101. Therefore, when forming the capping layer 17A, a thickness of the capping layer 17A formed on the sidewalls of the first pattern 101 becomes relatively small at the interface of the poly-Si layer 13 and the WN layer 14. Thus, as a result of etching the remaining poly-Si layer 13 to form the second pattern 102, there occurs a problem in that the sidewall of the interface of the poly-Si layer 13A and the WN layer 14 is exposed.
As the sidewall of the interface of the poly-Si layer 13A and the WN layer 14 is exposed, oxygen penetrates through the interface when performing the gate re-oxidation process, and thus, an insulation layer 19 including a tungsten oxide (WOx) or silicon oxide (SiOx) component may be generated. The insulation layer 19 increases the gate resistance, and thus, causes a problem such as a signal delay in a high-frequency operation.